1. Field of the Invention
The present invention relates to the field of high voltage pass gates in integrated circuits which generate the high voltage internally from a lower positive supply voltage. Specifically, the present invention relates to NMOS implementations of high voltage pass gates which exist for programming and erasing flash non-volatile memory devices.
2. Discussion of the Related Art
In flash memory integrated circuits, high voltages are generated on the chip for programming purposes. These high voltages (around 20V) are much higher than the highest supply voltage (around 3V), and are typically produced by large charge pumps. Because these charge pumps consume power and circuit area, it is desirable to minimize the total capacitance that these high voltage generators drive.
In most CMOS integrated circuits, PMOS transistors are used to pass the higher supply voltages, while NMOS transistors are used to pass the lower supply voltages. For example, PMOS transistors are used to implement pull up circuits, while NMOS transistors are used to implement pull down circuits. However, PMOS transistor subcircuits in a CMOS integrated circuit must be electrically isolated in an N-type well which must be biased at or above the same high voltage to guarantee that the P/N junction formed by the P-type drain/source regions of the PMOS transistors and the N-type well are not forward biased. If PMOS transistors are used in the high-voltage subcircuits, these N-type isolation wells constitute a very large capacitance for the on-chip high voltage generator to drive. Therefore, in high-voltage subcircuits supplied by on-chip high-voltage generators, the use of NMOS transistors is typically preferable to the use of PMOS transistors.
However, the voltage which can be passed by an NMOS transistor is limited by the transistor's threshold voltage Vt. If a gate voltage Vg is applied to an NMOS transistor's gate, then the maximum voltage which can be passed from source to drain is Vg-Vt. If the voltage generator produces a maximum voltage Vpp (about 20V), it is desirable for transistors passing or switching that high voltage to pass Vpp without incurring the threshold voltage drop. In other words, the pass transistors should pass Vpp rather than Vpp-Vt. Therefore, in order to pass a high voltage Vpp through an NMOS device, its gate must be boosted to a voltage higher than the high voltage by at least one threshold voltage Vt, so that Vpp+Vt must be applied to the gate of the NMOS pass transistor.
In a flash memory chip, the word lines of each block are controlled by a block decoder having NMOS pass gates which selectively pass the high programming voltage Vpp to one or more of the words in the block. A flash memory chip may have thousands of blocks, and therefore may have thousands of block decoders.
FIG. 1 illustrates a block decoder having a high voltage pass gate which is the subject of U.S. patent application Ser. No. 08/808,237, filed Feb. 28, 1997, and entitled "High Voltage NMOS Pass Gate For Integrated Circuit With High Voltage Generator", which is incorporated herein by reference in its entirely. CLK typically oscillates between ground and the positive supply voltage, which can be as low or lower than three volts. When CLK makes a transition from low to high, the voltage at node B correspondingly increases by Vcc*C1/(C1+CB), in which CB is the capacitance at node B. The capacitance at node B, CB, is the sum of the gate capacitance of transistors M1 and M5, the source of transistor M2, the drain of transistor M7, and the gate and drain capacitance of transistor M3, as well as the various routing capacitance associated with the wires connecting the various transistor elements connected to node B.
Discharge transistors M6 and M7 prevent nodes A and B from rising if the block is not selected by virtue of the DECODE signal being held to ground. Regulation transistors M3 and M4 discharge the nodes A and B when the high voltage Vpp is turned off at the end of a programming cycle.
Transistor M5 is typically large because it drives a high capacitance word line of a memory array. In the case of a NAND type flash memory array, the gates of several pass transistors may be connected to node B, as illustrated in FIG. 2, in which eight word lines wL0 through wL7 are connected by eight pass transistors M50 through M57 to eight potentially high voltage nodes xT0 through xT7, respectively. In this case, the capacitance CB on node B may be very large. The capacitance CB can be ten times larger than the gate capacitance of any of the transistors M1-M4.
Therefore, a need exists for a high voltage pass gate which is able to function as a block decoder in a NAND type flash memory circuit having high capacitance pass gate nodes. Because it is replicated many times on an integrated circuit, the block decoder circuit must not be overly large, and must provide acceptable output node rise times.